This thesis presents an FPGA-based SmartNIC design that offloads hot-data key-value (KV) access from the host to the network interface. The prototype is implemented on an AMD Alveo U45N SmartNIC using the OpenNIC shell and follows a dual-plane model: a host-side control plane (DPDK over PCIe/QDMA) performs \texttt{Insert} and \texttt{Delete} to populate and manage the on-card store, while a NIC-side data plane serves remote \texttt{GET} requests through a standard UDP/IP interface. To keep the lookup fast path self-contained and predictable, the NIC datapath integrates request parsing, hashing, allocation, and near-memory access as a fully pipelined hardware pipeline. Hot items are stored in on-chip BRAM/URAM (near-memory), avoiding host DRAM access and repeated PCIe transactions on the critical path.