The transition of Artificial Intelligence from cloud architectures to edge computing is accelerating, driven by the needs for data privacy, reduced latency, and operational cost-efficiency. Enabling complex workloads at the edge requires specialized hardware capable of intensive computation within a constrained energy environment. While existing solutions such as TPUs, FPGAs, and specialized microcontrollers address these needs, this master thesis proposes an alternative open-source approach: the integration of a Coarse-Grained Reconfigurable Architecture (CGRA) named R.A.C.E. (Reconfigurable Arithmetic Coarse-grain Engine) into a RISC-V ecosystem. CGRAs offer a compelling trade-off between the flexibility of general-purpose processors and the efficiency of dedicated ASICs. However, the communication overhead between the processor core and the accelerator remains a critical performance bottleneck.