Over the past two decades, the growing complexity of modern processor architectures, characterized by deep pipelines, speculative execution and intricate control logic, has shifted the critical challenge of hardware development from design to verification. This shift has increased the demand for more rigorous verification methodologies, leading to the widespread adoption of Formal Verification alongside traditional simulation. Formal Verification relies on mathematical techniques to exhaustively analyze the space of possible behaviors of a design, rather than computing results for particular input stimuli. Despite its strength, it is limited by the well-known state explosion problem, a phenomenon consisting in the exponential growth of reachable states, thus motivating the development of hybrid and semi-formal approaches.