Scalable silicon quantum processors require control electronics capable of generating low-noise RF tones and fast gate waveforms under severe cryogenic power constraints. This thesis presents the design of a cryogenic CMOS LC voltage-controlled oscillator (LC-VCO) in TSMC 65 nm planar process and its integration within a dedicated control-chip architecture targeting silicon spin-qubit operation. A top-down methodology is adopted: system-level requirements (frequency plan, tuning range, phase-noise limits, and power budget) are translated into tank specifications, tuning-network constraints, and active-core sizing to ensure reliable start-up and stable oscillation amplitude at cryogenic temperature. The VCO is then embedded into the chip-level system, addressing practical integration aspects such as bias generation and distribution, layout-driven parasitics, and interfaces with surrounding control blocks (e.g., waveform generation, multiplexing, and clock/frequency distribution).