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FPGA implementation, development and testing of synthesizable thermal, flicker and RTN noise System Verilog models

Arianna Presepi

FPGA implementation, development and testing of synthesizable thermal, flicker and RTN noise System Verilog models.

Rel. Mario Roberto Casu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2026