Open-source hardware ecosystems have enabled complete processor development flows, from HDL design to silicon tape-out. The VE-HEP project demonstrated an end-to-end open ASIC implementation based on VexRiscv, an open-source RISC-V processor written in SpinalHDL, and cryptographic components. In that design, however, a standardized physical TRNG was not integrated, leaving entropy generation reliant on custom implementations. This thesis contributes the integration of OpenTRNG's physical TRNG module into a VexRiscv-based System-on-Chip. The Verilog TRNG IP is wrapped as a memory-mapped peripheral within the existing SpinalHDL-based SoC architecture. Bare-metal firmware drivers implement initialization, status monitoring, polling, and entropy acquisition routines. System-level verification exercises complete CPU-to-peripheral transactions, validating both functional correctness and bus integration.