This thesis investigates the development of a comprehensive compliance veri- ??cation framework for a RISC-V RV32 processor, implemented using the Uni- versal Verification Methodology (UVM). The primary objective is to ensure the processor's strict adherence to the base RISC-V Instruction Set Architecture (ISA) specification through rigorous simulation and systematic comparison with the SPIKE reference model. The project encompasses the design and realization of a modular UVM test-bench capable of generating randomized instruction and data stimuli, monitoring execution behavior, and performing automated runtime checks. This environment enables the assessment of functional equivalence between the Device Under Test (DUT) and the golden reference model across a broad spectrum of instructions.