The continuous growth in complexity of modern digital systems and the rapid diffusion of the open RISC-V Instruction Set Architecture have made functional verification a fundamental step in the design flow. Ensuring that a processor behaves correctly under all possible operating conditions is increasingly challenging, and verification today often represents the largest share of the overall design effort. For this reason, advanced methodologies such as the Universal Verification Methodology (UVM) are essential to build reliable, reusable, and scalable verification environments. In this thesis, a UVM-based framework was set up to verify a RISC-V processor. The work focuses on the CV32E20 core from the OpenHW Group’s CORE-V family as the main reference and builds an environment that can handle both the base ISA and selected custom extensions.