Modern high-performance Out-of-Order processors rely heavily on Store-To-Load Forwarding to reduce load latency, placing significant timing pressure on the Store Buffer as the instruction window scales. The associative search logic in the Store Buffer, essential for identifying forwarding candidates, becomes a critical bottleneck, creating a scalability wall for larger designs. This thesis proposes and evaluates a Hierarchical Store Buffer as a solution to this challenge. This design decouples the Store Buffer’s functions by splitting it into two specialized structures: a Hazarding Store Buffer, which maintains all in-flight stores for precise hazard detection, and a smaller Forwarding Store Buffer, which mirrors a sliding window of recent stores to enable fast, low-latency Store-To-Load Forwarding.