This thesis presents the design of a fully digital Voltage Level Detector (VLD) architecture for dynamic read and write assist configuration in SRAM arrays. In advanced CMOS technologies, aggressive voltage scaling is essential for energy efficiency but compromises memory stability. To enhance reliability, assist circuits are commonly employed, whose activation depends on the supply voltage level. Traditionally, this level is monitored using analog voltage comparators, which suffer from poor scalability, high area and power overhead, and sensitivity to process variations. The proposed VLD architecture replaces analog comparators with a fully digital solution composed of three key components: a Dynamic Variation Monitor (DVM), which continuously evaluates the timing margin of a tunable delay path to indirectly sense voltage changes; an Auto-Calibration Circuit, which automatically adjusts the delay configuration to align the DVM's sensitivity with a specific voltage threshold, ensuring accurate detection across varying operating conditions; a Control Block that validates voltage transitions through a dual-signal mechanism.