Giorgio Iemmolo
Architectural Analysis and Performance Optimization of an I2C-to-AHB Bridge for RISCV DMA.
Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
Abstract
In a system, data exchange between two elements, each operating within its own clock domain, may present certain critical issues when one of the elements is busy executing another task or works at a lower frequency, thereby becoming unable to properly participate in the transmission of information. An example of this system, which is also the focus of this thesis, is composed of a Power Management Integrated Circuit (PMIC) and an external Application Processor (AP). PMIC, via a RISCV, monitors and manages the battery status of the device in which is integrated. This data is stored in internal RAM (which has an AHB interface), and the AP, through the I2C interface, can exchange this information by performing read and write operations.
However, the RAM can also be accessed by other components within the PMIC
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