This thesis investigates the design of approximate digital circuits with Gaussian error distributions, primarily targeting, but not limited to, Post Quantum Cryptography (PQC) applications. The growing importance of PQC in secure communications highlights the need for efficient and reliable arithmetic circuits. The primary objective of this research is to develop an architecture that integrates Gaussian noise directly into the design of an approx- imate adder, thus eliminating the need for external noise sources. Existing architectures of approximate adders in the literature primarily focus on sacrificing accuracy for efficiency, such as in area, power consumption or clock frequency, rather than on controlling the error distribution.