Giuseppe Salvatore Piazza
Subgraph Isomorphism: parallelizing dataflow of an FPGA based architecture.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
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Abstract
Subgraph isomorphism is a well-known NP-hard problem involving a large graph, referred to as the datagraph, and a smaller graph, known as the querygraph. In this context, both graphs have labeled vertices, and an isomorphism exists when one or more subgraphs of the datagraph contain nodes with labels that match those of the query graph’s nodes, and these nodes are connected by the same edges. Currently, numerous CPU-based algorithms are available for this matching process. To enhance speed, GPU-based algorithms can be considered; however, they demand significant power, especially when high-bandwidth communication channels are involved. To achieve lower power consumption while leveraging highly parallel architectures, an FPGA-based core may be a more effective solution.
In this thesis, the LESS architecture, developed using Vitis HLS for Xilinx Kria boards, is optimized through parallelization to enhance performance
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