Federica Bader
Design and integration of a RISC-V based accelerator for Ascon.
Rel. Guido Masera, Maurizio Martina, Alessandra Dolmeta. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
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Abstract
Ensuring privacy and data protection has become a paramount concern nowadays, especially in constrained devices that, due to their nature, are not able to implement complex standard cryptographic algorithms. This is the field of lightweight cryptography, algorithms made specifically to balance security with efficiency, ensuring that all systems can safeguard data without hindering performance. The newly appointed standard is the Ascon family, which is a group of algorithms that share the same core function to perform a variety of functions, spanning from authenticated encryption with associated data (AEAD) to hashing and extendable output functions (XOF). This work is focused on improving the performance of Ascon algorithms, through the design in steps of a customized accelerator.
The first optimization is performed through an instruction set extension of a generic RISC-V processor, iteratively finding out the bottlenecks of the algorithm and solving them
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