UVM testbench development for I2S protocol verification
Davide Ferraro
UVM testbench development for I2S protocol verification.
Rel. Maurizio Martina, Alessio Pelle, Sandro Sartoni. Politecnico di Torino, Master of science program in Electronic Engineering, 2024
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Abstract
Modern digital integrated circuits are increasingly becoming more and more complex, with several internal logic blocks, submodules and interconnections. Not only the functionalities they implement are quite complicated, but they must perform their tasks with stringent timing, area and power requirements. Due to these reasons, verification of integrated circuits is becoming more important. Thanks to the verification process, it is possible to make sure that new devices behave according to their specifications in a timely manner, reducing the time to market. Moreover, it allows to significantly shrink the number of bugs reaching the physical production stage of chips, preventing costly manufacturing errors and increasing the product reliability.
The introduction of the Universal Verification Method (UVM) has drastically changed the way verification is carried out, introducing a standardized, robust, modular and flexible environment, enhancing the interoperability and facilitating the exchange of code between different teams and projects
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