With the unstoppable demand for smaller, faster, and more energy-efficient electronic devices, the semiconductor industry faces a critical challenge: the continued scaling of transistor dimensions to uphold Moore's Law. Nevertheless, the downscaling limitations of conventional planar transistors require the investigation of other device structures. Because of their excellent electrostatic control and intrinsic scalability, junctionless nanowire transistors (JNT) present a feasible solution and are highly desirable for use in next-generation electronics. Due to their reduced dimensions, the Si nanowires guarantee better controllability and increased sensitivity. The key factor that characterizes the JNTs is the absence of pn-junctions. This provides several benefits, such as an easier fabrication process since the devices do not require abrupt doping profiles within the nanowire channel.