Over the past five decades, there has been a continuous increase in computing efficiency, driven by both transistors’s size and voltage scaling. This allowed to enhance the complexity, the parallelism of the architectures and to comply with the limited energy of edge devices. However, nowadays CMOS seems close to its technological limit because of the progressive increasing of the leakages attributed to the Boltzmann Tyranny that brought to the end of Dennard’s law. In this context, non volatile spintronic devices are promising solutions to address the challenges currently faced by CMOS technologies. Despite that, all spintronic devices currently available on the market are primarily used for memory applications.