A problem that engineers often face at the end of the physical design flow consists in some paths in their design violating the given timing constraints. EDA tools whose purpose is fixing these violations do exist and are frequently employed, but they are not able to significantly speed up paths with specific properties: in these cases manual intervention by the engineers is needed. These paths that cannot be automatically fixed by the aforementioned tools, which will be referred to as Non-Automatically-Fixable Paths (NAFiPs for short), are characterised by the fact that they contain poorly routed nets or high-delay memories (like RAMs) and need very targeted fixes.