Spike detection circuit adaptation and optimization for ensuring safe operating testing conditions on Silicon Carbide power mosfet

Simone Pallante

Spike detection circuit adaptation and optimization for ensuring safe operating testing conditions on Silicon Carbide power mosfet.

Rel. Marcello Chiaberge. Politecnico di Torino, Corso di laurea magistrale in Mechatronic Engineering (Ingegneria Meccatronica), 2024

Abstract

This research proposes and evaluates an adaptation circuit to allow spike free testing on power discrete devices with one of the SPEA’s test cell. The objective of this device is to increase the confidence level of the manufacturers of wideband power MOSFETs on the expected lifetime of the devices tested by ensuring testing under conditions that do not wear the oxide layer significantly. The study consists of 3 consequential parts: the first one is the state of the art on the SPEA test cell to understand possible limitations due to the physical and link layers characteristics of the test cell itself.

Moreover, during this part, a deep investigation on the state of the art of wideband semiconductor devices wear mechanisms is carried, with a focus on silicon carbide MOSFET devices which is the technology for which this device has started to be required in the first place