Aditya Garg
Analysis and Mitigation of Single Event Transients (SET) effect on RISC-V based FPGA.
Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2024
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Abstract
In the rapidly evolving field of electronics, Field-Programmable Gate Arrays (FPGAs) have emerged as a cornerstone technology for a wide range of applications, from consumer electronics to critical aerospace systems. The versatility and programmability of FPGAs, combined with the increasing demand for low-power, high-performance computing, have led to the widespread adoption of Reduced Instruction Set Computing (RISC) architectures, notably the RISC-V, within FPGA designs. This open-source architecture offers significant advantages in terms of customization, scalability, and efficiency, making it an ideal candidate for integration into FPGA platforms. However, the deployment of RISC-V based FPGAs in radiation-prone environments, such as space, raises substantial reliability concerns due to the potential effects of radiation-induced errors.
Radiation effects on semiconductor devices can lead to a myriad of operational challenges, including transient faults, permanent damage, and functional disruptions
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