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Development of a hardware module for online learning on spiking neural networks with partial reconfiguration on FPGA.

Liqi Zeng

Development of a hardware module for online learning on spiking neural networks with partial reconfiguration on FPGA.

Rel. Stefano Di Carlo, Alessandro Savino, Alessio Carpegna. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024

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Sviluppo di un modulo hardware per l’apprendimento online su reti neurali spiking con riconfigurazione parziale su FPGA. abstract This article introduces the design and implementation of a new hardware module designed to support online learning of spiking neural networks (SNN) and its partial hardware reconfiguration on the Xilinx Artix-7 FPGA platform. The spiking neural network can simulate the unique way of exchanging information in the form of electrical pulses between neurons in the biological brain. It is widely considered to be an ideal choice for embedded hardware implementation due to its low energy consumption and small size. This study ensures that the STDP (Spike Timing Dependent Plasticity) learning algorithm implemented in hardware performs consistently with its simulation in Python. Subsequently, this paper deeply explores the impact of quantization level on learning accuracy and compares different approximate implementations of STDP, aiming to evaluate the specific impact of various calculation methods on the final performance. Such evaluation is crucial for optimizing the area and power consumption of SNN hardware modules. It aims to improve the overall performance and application applicability of the SNN model through fine adjustments and provide a resource-efficient. As part of this research, this hardware module combines key components such as the ARE decoder, temporary buffer queue and calculation conversion unit, allowing it to dynamically interact and update the SNN weight data stored in BRAM. This not only significantly improves the flexibility and efficiency of the online learning process, but also ensures the scalability and adaptability of the system by optimizing resource allocation. The ultimate goal of this project is to deploy a comprehensive, partially reconfigurable SNN hardware accelerator on the Xilinx Artix-7 FPGA platform that can adapt to changing application requirements, support uninterrupted online learning, and be flexibly adjusted as needed Hardware resource configuration. Through the results of this research, we expect to promote the development of intelligent systems to a higher level in terms of adaptability and energy efficiency ratio, especially in application scenarios that have strict requirements on performance and energy consumption.

Relators: Stefano Di Carlo, Alessandro Savino, Alessio Carpegna
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 70
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/30990
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