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Development of System Verification Methods for Aircraft Electronic Systems

Lucia Vencato

Development of System Verification Methods for Aircraft Electronic Systems.

Rel. Mario Roberto Casu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2024

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In aviation industry, it is essential to guarantee the safety and reliability of aircraft equipment since hardware failures can have disastrous effects. As a consequence, the verification process is indispensable, providing a methodical and rigorous approach to ensure that hardware components meet specified requirements and adhere to stringent safety guidelines. This thesis work was conducted in Leonardo Electronics in the context of hardware verification. The primary objective of this research is to study and explore the Universal Verification Methodology (UVM), with the goal of developing a comprehensive testbench for a Universal Asynchronous Receiver/Transmitter (UART) transmitter device. UVM relies on System Verilog language, which exploits Object-Oriented Programming constructs, and includes a set of pre-defined classes and methods that allow to create scalable, reusable, and maintainable verification environments. Initially, the primary UVM components were chosen, and the testbench infrastructure was developed using Siemens EDA's UVM Framework (UVMF) code generator. UVMF requires configuration files, written in yaml language, to create the testbench. Therefore, each component was correctly described following yaml guidelines. After obtaining the basic testbench, further modifications were implemented to customize the behavior of individual components in order to meet the specific requirements of the Device Under Test (DUT). The developed testbench includes different UVM components: an agent responsible for transmitting input data to the DUT, a second agent tasked with collecting output data from the DUT, a predictor utilized for calculating the golden output values, and a scoreboard utilized to verify the correspondence between the golden values and the actual outputs. Simulations were conducted to verify the correct behaviour of the developed testbench and to test the uart transmitter device under various configurations. QuestaSim and Visualizer, provided by Siemens EDA, were the software tools used to run simulations.

Relators: Mario Roberto Casu
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 53
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: LEONARDO SPA
URI: http://webthesis.biblio.polito.it/id/eprint/30944
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