In aviation industry, it is essential to guarantee the safety and reliability of aircraft equipment since hardware failures can have disastrous effects. As a consequence, the verification process is indispensable, providing a methodical and rigorous approach to ensure that hardware components meet specified requirements and adhere to stringent safety guidelines. This thesis work was conducted in Leonardo Electronics in the context of hardware verification. The primary objective of this research is to study and explore the Universal Verification Methodology (UVM), with the goal of developing a comprehensive testbench for a Universal Asynchronous Receiver/Transmitter (UART) transmitter device. UVM relies on System Verilog language, which exploits Object-Oriented Programming constructs, and includes a set of pre-defined classes and methods that allow to create scalable, reusable, and maintainable verification environments.