Marco Massetti
Exploring the Razor Approach for Better Than Worst-Case Design in Latency-Insensitive Digital Circuits.
Rel. Luciano Lavagno, Filippo Minnella. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023
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Abstract
The relentless advancement of technology in recent years has led to an exponential growth in the demand for computing power across various sectors. From artificial intelligence to data analytics and complex simulations, the computational requirements have consistently pushed to the limit the capabilities of existing hardware. In the last years digital circuits have meet these performance requirements by architectural improvements and by technology scaling, but as semiconductor technology continues to shrink and more transistors are integrated on a single chip, power dissipation has emerged as a critical bottleneck. Moreover, as feature sizes continue to shrink, the sensitivity of circuit behavior to small deviations in manufacturing processes, supply voltage, and operating temperature (PVT variations) becomes more pronounced.
This poses a formidable challenge for circuit design, as the traditional design methodologies that rely on worst-case scenarios may result in sub optimal performance or excessive power consumption due to its overly conservative nature
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