The growing gap between the performance of memories and processors over time has resulted in the well-known problem often called the “Memory-wall”. This term refers to the performance degradation issues stemming from the classical von-Neumann computational paradigm, where the cpu and memory are separated. Especially for data-intensive applications, the continuous transfer of data between these two causes high power consumption and increased execution times. A possible solution to this problem is represented by the Logic in Memory (LiM) paradigm. The LiM architecture integrates computational elements inside the memory array, enabling the parallel processing of data and reducing data movement between the processor and memory.   This thesis considers a new type of LiM architecture called GP-LiMA(General Purpose Logic-in-Memory Architecture) pre-developed at the VLSI Laboratory of Politecnico di Torino.