Assessing the Logic-in-Memory paradigm within a RISC-V framework 

The growing gap between the performance of memories and processors over time has resulted in the well-known problem often called the “Memory-wall”. This term refers to the performance degradation issues stemming from the classical von-Neumann computational paradigm, where the cpu and memory are separated. Especially for data-intensive applications, the continuous transfer of data between these two causes high power consumption and increased execution times. A possible solution to this problem is represented by the Logic in Memory (LiM) paradigm. The LiM architecture integrates computational elements inside the memory array, enabling the parallel processing of data and reducing data movement between the processor and memory.   This thesis considers a new type of LiM architecture called GP-LiMA(General Purpose Logic-in-Memory Architecture) pre-developed at the VLSI Laboratory of Politecnico di Torino. GP-LiMA is a general-purpose LiM Architecture that integrates processing functionalities within each memory row, the ensemble of memory row and related processing unit is referred to as smart block. This also facilitates internal data transfer, eliminating the need for data to be fed to the processor. As a result, it aims at reducing the time the processor spends on data transfer and instruction execution, along with the associated power consumption.  This thesis work aims at integrating GP-LiMA within a RISC-V based system using it as an accelerator connected to the processor, thus exploring the associated benefits and challenges. To enable the connection of GP-LiMA to Ri5cy, two modules have been designed. A controller is needed to receive request signals from the RiscV and translate them into configuration and GP-LiMA request signals, depending on whether it should be used as standard memory or as LiM. A switch used to multiplex signals from the RiscV to the memory or the GP-LiMA based on the sent address. Thanks to the added modules, the processor can access GP-LiMA as a standard memory with read and write operations, but it can also start the execution of an algorithm inside GP-LiMA. Hence, a special GP-LiMA address is reserved to serve as trigger for starting the execution.  Several tests have been conducted to evaluate the speed-up benefits provided by the integration of GP-LiMA. Suitable algorithms have been run on both Ri5cy-only and Ri5cy+GP-LiMA systems, thus allowing the assessment of such comparison.also by checking the execution of more complex algorithms like CNN LeNet-5 (Convolutional Neural Network). LeNet-5 was one of the early models of convolutional neural network algorithm that comprises 16x16 pixel grayscale images, the algorithms execute by the GP-LiMA consists of the first layer of convolution.  Several tests have been conducted to evaluate the speed-up benefits provided by the integration of GP-LiMA. Suitable algorithms have been run on both Ri5cy-only and Ri5cy+GP-LiMA systems, thus allowing the assessment of such comparison. This work paves the way for future advancements in LiM design and its practical application in real-world computing systems.