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A Microprocessor with customizable Instruction set to improve performance and power consumption

Daniele Crimi

A Microprocessor with customizable Instruction set to improve performance and power consumption.

Rel. Maurizio Martina, Claudio Sinisi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

Abstract:

The thesis work focuses on the improvement of a RISC-V RV32IM-compatible core and, in particular, into the development of a custom standard-compatible extension to improve performance and power consumption. The target for the extension's design is an encryption algorithm. A work flow for design, testing and estimations of timing, area and power is provided leveraging on the following set of tools: - A Digilent Nexys DDR4 FPGA board for the implementation; - Desing Suite and Toolchains (Vivado, Visual Studio Code, GNU makefile, GCC); - Multiple languages for hardware descritpion, programming and scripting (systemverilog, VHDL, python, C, bash).

Relators: Maurizio Martina, Claudio Sinisi
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 87
Additional Information: Tesi secretata. Fulltext non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: CAPGEMINI ITALIA SPA
URI: http://webthesis.biblio.polito.it/id/eprint/29371
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