The rapid advancement of technology, coupled with the widespread adoption of the Internet of Things (IoT), has driven the quest for novel solutions that significantly improve speed and resource efficiency, surpassing traditional implementations. In hardware design, High-Level Synthesis (HLS) techniques present an efficient avenue for generating hardware designs using high-level programming languages, notably C/C++. HLS tools scrutinize design specifications and autonomously create hardware implementations aligned with performance requirements. The main objective of our research was to accelerate the 3GPP 5G Channel Model. We specifically aimed at enhancing the channel model using High-Level Synthesis (HLS) tools designed for Xilinx and Intel FPGA platforms.