This thesis looks into the topic of "Delay Control with Programmable Data Planes". The primary focus is on exploring the potential of programmable switches, specifically BMv2 switches programmed with the P4 language. By investigating the operations that can be performed inside switch pipelines, the thesis aims to provide a deeper understanding of how to control the delay of packets in the network. Through our attempts, we observed that recirculation within the programmable switch is a potential method for controlling packet delays across the network. In the following, I developed packet recirculation within programmable switches. Based on the development of packet recirculation, this study investigates the effect of different recirculation iterations on packet delay.