The decades-long strategy of transistor downscaling for miniaturization and improved power-performance-area (PPA) is facing limitations beyond front-end of line (FEOL) elements. Shrinking back-end of line (BEOL) interconnects leads to resistance (R) and capacitance (C) issues, causing delays that hamper design performance. Understanding routing and its correlations to design criteria is crucial. PnR results hold data on path details, but extraction flows are needed to access this. Extracting data is vital for analyzing and optimizing chip designs to tackle contemporary technological challenges. The aim of this project is to improve, extend, and increase the features of the existing extraction flow which captures and connects the exact topology of paths from a signoff database to other circuit features and physical parameters of a given chip design, node, and technology.