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Serial bit accelerator with sparsity managment

Francesco Dilevrano

Serial bit accelerator with sparsity managment.

Rel. Maurizio Martina, Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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Abstract:

This thesis work starts with an explanation of what are neural networks and the reasons for their big exploitation in recent years. Then there is a focus on particular architecture choices that make some NN faster and more efficient. Particular attention should be paid to the compression method for sparsity. Starting from a previously developed engine some modifications have been applied to it in order that the engine able to skip useless operations and so improve the throughput. The main modifications are the introduction of a filtering system to manage compression methods and some modifications to adapt the Multiply and Accumulation process.

Relators: Maurizio Martina, Guido Masera
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 65
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/28524
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