The acceleration of Neural Network (NN) algorithms became in recent years an important research topic. Among possible approaches, having different tradeoffs, this thesis focuses on implementing a Precision Scalable (PS) multiplier to be placed inside the pipeline of the Ibex low-power RISC-V processing core. PS multipliers are multipliers capable of executing more than one multiplication (MUL) in parallel in case these operations are at a lower precision than the maximum one the multiplier can support. Target for this architecture is the acceleration of Quantized Neural Networks (QNN). QNNs are an optimization of standard NNs, which uses only integer operations, to ease the deployment specifically on low-power performance-constrained devices, that is the use target of the Ibex core.