Integrated electronics industry, since early 70s, realized how increasing the transistors integration density was the key to push towards the performances in CMOS technology. The notorious Moore’s law chronicled, for almost fifty years, the evolution of chip industry. The main strategy to improve switching frequency, power dissipation and area was typically the constant field scaling approach traced out by Dennard et al. at IBM in 1974 which was based on keeping the electric field constant by scaling down device geometry and supply voltage by a constant factor to keep reliability unaltered and improving current capability. In more aggressively scaled nodes the short channel effects (SCE) compromised the feasibility of this approach leading to unbearable subthreshold leakage in planar MOSFETs.