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A RISC-V based accelerator for NFC Signal Processing

Francesco Babbaro

A RISC-V based accelerator for NFC Signal Processing.

Rel. Guido Masera, Stefan Brennsteiner. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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Near Field Communication (NFC) is an ubiquitous technology with many applications ranging from identification to ticketing, from mobile payment to logistical solutions and, just recently, wireless charging. Every modem unit must be able to support multiple communication standards in different operative conditions. In many cases, this is achieved by means of an extensive use of custom DSP logic at the expense of full functional flexibility and of an high engineering effort, which could be unacceptable from the business perspective. One way to balance chip-resources with the growing need for flexibility is to consider the adoption of RTL microprocessors able to perform DSP instructions. They provide the wanted flexibility at the cost of potentially higher resource usage and clock rates in order to meet the end-application performance. In this context, starting from an open-source RISC-V based core by OpenHW group, a DSP hardware accelerator has been designed and tested. The work has been carried out in parallel with a colleague who focused on the software/algorithmic part to be run on the developed hardware. From the interaction of the software/hardware aspects, the two parts have been improved and tailored during the months. The accelerator implements an architecture for the efficient execution of digital filtering, which turned out to be the main limit within the considered application. The keyword is flexibility, giving to the user deep customisation possibilities, without impacting significantly on the efficiency. The coupling with the main core is achieved through a standardised interface by OpenHW, provided natively by the chosen core, allowing an easier instruction set (ISA) extension. This work represents the starting point for a more ambitious project that will be carried out in the next years. The outcome is promising, resulting in performance close to the target and reasonable area-power requirements. However, assumptions and limitations have been considered in this stage, therefore a lot of investigations and work are needed to get, eventually, a working system.

Relators: Guido Masera, Stefan Brennsteiner
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 125
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: NXP Semiconductors Austria GmbH & Co KG (AUSTRIA)
Aziende collaboratrici: NXP SEMICONDUCTEURS
URI: http://webthesis.biblio.polito.it/id/eprint/25487
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