Simone Emiliani
Design and Benchmarking of Low Power, Low Noise and Rad-Hard Comparators for Hybrid Pixel Detector for the Large Hadron Collider Upgrade.
Rel. Gianluca Piccinini. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2022
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Abstract
Hybrid pixel detectors allow to optimize separately the sensor matrix and the readout Application Specific Integrated Circuit (ASIC). Although the use of this type of detectors was extended to other fields of science by the Medipix collaboration, it is still employed at CERN (the European Organization for Nuclear Research) to assemble trackers for the Large Hadron Collider (LHC) experiments. The electronics associated to CERN detectors operates in a harsh environment, because of high levels of radiation and high magnetic field. LHC detecting systems are constantly object of upgrades to improve their performances in terms of speed, resolution and power consumption. To this end, CERN microelectronics section recently choose a 28nm bulk CMOS technology replacing older nodes in order to develop the next generations of read out ASIC.
Thanks to the advantages of miniaturized transistors, a new prototype chip named PicoPix is under development with the aim to achieve a time resolution lower than 30ps for large input charges
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