This thesis explores a novel approach to on-chip data processing and readout in pixel imagers based on embedded processors for High Energy Physics applications. This subject represents a new field of development posing new challenges both at the system and implementation levels. The first part of the thesis proposes a methodology to evaluate the performance of a Network-on-Chip (NoC) connecting several processing elements. Network latency has been studied taking into consideration several input parameters and different topologies. The maximum sustainable particle rate before the system diverges has also been analyzed. Such a methodology can be used to compare distributed solutions based on NoC to single-processor solutions and help define the readout architecture for the pixel imagers.