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On-Chip Processing for Pixel Imagers in a 28nm technology for HEP application

Jashandeep Dhaliwal

On-Chip Processing for Pixel Imagers in a 28nm technology for HEP application.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2022

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This thesis explores a novel approach to on-chip data processing and readout in pixel imagers based on embedded processors for High Energy Physics applications. This subject represents a new field of development posing new challenges both at the system and implementation levels. The first part of the thesis proposes a methodology to evaluate the performance of a Network-on-Chip (NoC) connecting several processing elements. Network latency has been studied taking into consideration several input parameters and different topologies. The maximum sustainable particle rate before the system diverges has also been analyzed. Such a methodology can be used to compare distributed solutions based on NoC to single-processor solutions and help define the readout architecture for the pixel imagers. The second part studies embedded processors for on-chip data processing and readout. Given the limited power, area, and latency budget available for High Energy Physics applications, general-purpose processors are typically too slow or power and area hungry. For this reason, the concept of Application Specific Instruction-set Processor (ASIP) has been introduced for the first time in the field of High Energy Physics. The objective is to demonstrate a workflow to design a processor from the Instruction Set Architecture (ISA) and micro-architecture to its physical implementation. In addition, functional verification and profiling require the development of an application-specific test code providing measurements of cycle count, instruction, and functional utilization. Finally, a complete RTL-to-GDS implementation flow in a 28 nm CMOS technology provides the relevant figures of merit regarding achievable frequency, area occupation, and power consumption completing the evaluation and enabling further optimization. This project establishes the first exploratory study for both Network-on-Chip and ASIP applied to on-chip data processing and readout for future experiments in High Energy Physics.

Relators: Guido Masera
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 126
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: CERN (SVIZZERA)
Aziende collaboratrici: CERN
URI: http://webthesis.biblio.polito.it/id/eprint/24777
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