The Cascaded-H-Bridge (CHB) converter has been demonstrating over the last years to be an adequate multilevel topology for high power applications. The full-bridge structure of the sub-modules (SMs) offers a degree of freedom that may be exploited with the modular topology in order to achieve a higher closed-loop control bandwidth at parity of same switching frequency. The goal of the master thesis is to design and test the proposed Sequential Phase-Shifted PWM (PS-PWM) algorithm, which should be capable of improving the equivalent sampling and update frequency of a CHB multilevel converter by sequentially commanding the cascaded cells.