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A multi-technology hardware-aware layout synthesis library for quantum circuits compilation

Andrea Russo

A multi-technology hardware-aware layout synthesis library for quantum circuits compilation.

Rel. Mariagrazia Graziano, Giovanna Turvani, Maurizio Zamboni. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

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Nowadays, quantum algorithms are designed using an idealised high-level quantum circuit description without considering the quantum hardware characteristic. Unfortunately, in the contemporary Noisy Intermediate-Scale Quantum (NISQ) computer era, the execution on real devices strongly depends on the physical properties of the backend. Quantum compilation toolchains aim to refine the original quantum circuit description, making it executable on the target hardware while optimising some desired figure of merits. This process is composed of two steps: the logic synthesis, decomposing the original circuit using the target technology native gates, and the layout synthesis, solving the coupling-constraints of the target NISQ device, due to the hardware limitations. This latter phase consists of two sub-steps: the placement, mapping the logical qubits used for describing the quantum algorithm to the physical qubits of the NISQ device, and the routing, ensuring that each two-qubit interaction is allowed. Indeed, swap gates are added to make the final circuit compliant to the target coupling-graph. The aim of this thesis is twofold: developing a flexible multi-technology library to perform the layout synthesis phase, and integrating it inside the template-based compilation toolchain available at the VLSI Lab of Politecnico di Torino. The library is written entirely in Python, targeting quantum circuits described using the OpenQASM 2.0 language. The supported technologies are: superconducting qubits, quantum dots (partially connected), Nuclear Magnetic Resonance (NMR) and trapped ions (fully connected). Being the layout synthesis a search and optimisation problem, exact and heuristic strategies are applicable. The latter were selected, having scalability as a main concern. The most promising heuristics implemented improve and broaden the field of application of a hardware-aware method available in the scientific literature. This algorithm exploits the execution time and error rates of native gates of a quantum device during the swap insertion phase. For the placement, three strategies were implemented: a trivial technology-agnostic one, and two strategies using simulated annealing to find a potentially optimal solution. The first aiming to find the sub-graph of most connected physical qubits in the target hardware, the latter exploiting the quantum gates features to find an optimal hardware-aware placement. For the routing phase the implemented solutions are: a basic hardware-unaware strategy, the original hardware-aware algorithm (adapted to target all the supported technologies), and an extended version of the latter, to target fully-connected topologies. This adaption was required for NMR and ion trap devices. Specifically, a modified version of the original method was devised, allowing it to shift the two-qubit interactions towards the stronger interacting nodes, to optimise the output circuit. Finally, the divergence between the discrete probability distributions of the measured eigenstates, before and after applying each implemented heuristics, is computed to prove the functional equivalence and validate the methodology. The integrated procedures are benchmarked against IBM’s Qiskit and Cambridge Quantum Computing’s TKET compilation toolchains, exploiting the figure of merits routinely used for the comparison in the associated literature: the number of swap gates added and the execution time and fidelity of the final quantum circuit.

Relators: Mariagrazia Graziano, Giovanna Turvani, Maurizio Zamboni
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 180
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/23553
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