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An Hyper Dimensional Classifier for Dynamic Vision Sensors

Raffaele Di Placido

An Hyper Dimensional Classifier for Dynamic Vision Sensors.

Rel. Marco Vacca, Guido Masera, Fabrizio Ottati. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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Hyperdimensional computing (HDC) is a neural inspired computing paradigm derived from the cognitive model proposed by Pentti Kanerva in 1988. Hyperdimensional computing consists in representing data through pseudo-random ultra-wide vectors, thus referred as hypervectors, with independent and identically distributed (i.i.d) components. A typical dimension (D) of an hypervector is D = 10000. The high dimensionality comes from the human brain complex structure which uses billions of synapses and neurons. Hyperdimensional computing is employed to compute similarity between data. Hence, an encoding phase is needed to transform data into hypervectors. Two are the main encoding methods, the record-based method and the N-gram based method. Both of them requires a memory called Continuous Item Memory (CiM) which stores Levels Hypervectors (L), i.e. hypervectors which represent the value of an input variable. Many works regarding hyperdimensional computing revolves around reducing the encoding module complexity, with particular attention into reducing the memory footprint of the CiM. Hypervectors can be either binary, i.e. each of their dimensions is represented as a bit that can take a single value between ¿1¿ or ¿0¿, or non-binary, if their elements are integers or floating point. In the binary case, an hypervector is defined as dense if the number of ¿1¿ and ¿0¿ is the same, while an hypervector is defined as sparse if ¿1¿-bits are present with a lower percentage than ¿0¿-bits. Researches on human brain functionality inspired not only cognitive algorithms, but also novel types of sensors. In this thesis, particular attention is given to a type of bio-inspired sensors called Event cameras. Differently from standard frame-based cameras, images with event cameras are not captured at a constant frame. Instead, event cameras report changes in brightness in asynchronous way. This results in acquiring images with lower latency. In this thesis, an hardware accelerator based on hyperdimensional computing with dense and binary hypervectors is implemented to classify images acquired with a type of event cameras called Dynamic Vision Sensors (DVS). The dimensionality for the hypervectors is D = 8192, while a record-based approach is used for the encoding phase. To reduce the dimension of the CiM, a single Seed Hypervector is manipulated to obtain the other Level Hypervectors instead of storing them. The design is validated on the N-MNIST dataset, while features of images are represented with Histograms of Averaged Time Surfaces (HATS). The design is also tested on FPGA, with the Xilinx Virtex-7 200T FPGA as the target architecture. Since not all architecture can handle the whole hypervector given the high-dimensionality, the hardware design is serialized in order to process parts of hypervectors at different times. The design is hence configurable, i.e. the number and the size of the hypervector chunks can be user defined. In particular, the algorithm can be configured to process hypervectors divided from 8 parts with 1024 bits each, to 1024 parts with 8 bits each. Thanks to Xilinx Vivado software, measurements of power, latency and resources utilization were extracted from the Xilinx Virtex-7 200T FPGA with four different configuration of the design: 64x128, 32x256, 16x512, 8x1024. In order to assert the low hardware requirements of HDC, the four configurations were also implemented on FPGAs from different families: Spartan-7, Aritx-7, Kintex-7 and Virtex-7.

Relators: Marco Vacca, Guido Masera, Fabrizio Ottati
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 133
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/23551
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