Politecnico di Torino (logo)

Logic-In-Memory implementation on FPGA

Coralie Marie Allioux

Logic-In-Memory implementation on FPGA.

Rel. Mariagrazia Graziano, Massimo Ruo Roch, Giovanna Turvani. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (19MB) | Preview

Nowadays, the Von Neumann architecture is the most used for microprocessors. This architecture comprises two main components: the processing unit and the memory. However, it introduces the memory bottleneck problem due to the huge difference of performance: modern processing units are incredibly faster than memories, requiring a considerable amount of energy and time to transfer the data between those two entities. Recently, the Logic-in-Memory (LiM) has been widely studied in the literature, aiming at solving this bottleneck. This paradigm merges the processing unit and the memory by placing directly some logic circuits inside or near the memory, consequently lowering the data exchange between those components and drastically reducing energy and time. In this thesis, a specific LiM implementation on FPGA of the XNOR-net, a bitwise convolutional neural network, is presented. The XNOR-Net is a viable choice thanks to its high parallelism potential. Specifically, the FPGA directly communicates with a MCU embedded on the same board, thanks to a protocol using the common IOs: thus, allowing the emulation of a real Von Neumann system, exploiting the LiM as a co-processor. The main objective around this implementation is to estimate the impact of the LiM paradigm on a real evaluation board by performing measurements on the circuits: in particular, timing, power and area occupation on the FPGA. To reach that goal, these measurements are also performed on an MCU-based implementation of the XNOR-Net, then analyzed and compared with the LiM ones. The results highlight the LiM tradeoff, as it achieves better performance in terms of timing and energy with respect to the MCU-based implementation, at the cost of an improved area footprint.

Relators: Mariagrazia Graziano, Massimo Ruo Roch, Giovanna Turvani
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 118
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/23547
Modify record (reserved for operators) Modify record (reserved for operators)