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Hardware Design of a Homomorphic-like Encryption Scheme for Spiking Neural Networks

Gianluca Menditto

Hardware Design of a Homomorphic-like Encryption Scheme for Spiking Neural Networks.

Rel. Guido Masera, Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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The last decades have seen a significant development of Artificial Neural Networks (ANNs). These advancements have enabled the application of ANNs to various domains, such as handwriting and speech recognition, or classification and computer vision tasks. However, the high power effort required by these NNs has pushed the research toward the low power domain. A new paradigm of NNs named the Spiking Neural Networks (SNNs) has demonstrated promising results in terms of performance and efficiency. Moreover, the success of NNs lies on the great availability of data, which may contain sensitive information. Hence, it is challenging from the privacy perspective to maintain the confidentiality of data. An efficient solution is represented by the Homomorphic Encryption (HE), a cryptographic method that allows performing computations over encrypted data instead of its raw version. The data owner encrypts the data and sends them to an SNN to obtain an encrypted prediction. The application of HE to NNs leads to ensure privacy both on the data and on the prediction since only the data owner can access their actual value. On the other hand, such privacy-preserving property of HE leads to energy and performance inefficiency. The high computational intensity of the encryption and decryption operations, as well as the computations in the encrypted domain, make NN systems slow and complex. In this thesis the design of a SHE system for SNNs using the Brakerski-FanVercauteren (BFV) scheme is conducted. In particular, the implementation of the SHE algorithms is carried out partially in Python and partially in VHDL. The whole design is simulated with Modelsim to test its correct behaviour and it is synthesized with Synopsys Design Compiler to evaluate its performance and efficiency.

Relators: Guido Masera, Maurizio Martina
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 108
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/23478
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