This work describes a methodology that could be integrated as an additional step into the ASIC design-flow for the development of cryptographic devices. The proposed methodology aims at testing the hardness of an ASIC architecture against Power Analysis Attacks (PAA) by executing the attack using power traces obtained from simulations. The tools used to retrieve them have been QuestaSim and PrimeTime and the process has been fully automated due to the large number of simulations needed. The target architecture has been a vector by circulant matrix multiplier which is frequently used in hardware implementations of Post Quantum Cryptography (PQC) decoding and encoding algorithms.