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HLS techniques for high performance parallel codes in Logic-in-Memory systems

Alessio Naclerio

HLS techniques for high performance parallel codes in Logic-in-Memory systems.

Rel. Mariagrazia Graziano, Giovanna Turvani, Maurizio Zamboni. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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In recent years, several researches have been conducted at the VLSI Laboratory of Politecnico di Torino on Logic-in-Memory (LiM) systems. This type of architectures aims to overcome the drawbacks due to the performance gap between CPU and memory, usually referred to as Von Neumann Bottleneck, by integrating simple computational units inside the memory cells. The regular structure of LiM arrays also allows for efficient parallel processing. Octantis is a High-Level Synthesis (HLS) tool for the exploration of LiM systems. It analyzes a C algorithm and generates a LiM architecture optimized for its execution, through the typical steps of HLS. The allocation phase collects user-defined constraints, the scheduling assigns to each instruction an execution time and the binding performs the mapping of operations on a LiM system. Finally, the code emission phase produces the description of the synthesized circuit through configuration files for DEXiMA, a LiM simulator developed in the same research context that characterizes the circuit in terms of space occupation and static and dynamic power consumption. This thesis addressed the expansion of the set of C structures compatible with the input specifications of Octantis. The work brought innovations to all the synthesis stages, which evolved to allow the program to explore even more complex architectural solutions. New techniques have been introduced to manage algorithms that use multiple array accesses inside nested loops, thus enhancing Octantis loop unrolling capabilities, that suits perfectly the intrinsic parallel nature of LiM units. In particular, a new module named InfoCollector has been developed with the purpose of gathering data relating to loops and pointers, towards the identification of arrays access patterns, i.e. the order in which the elements of an array are visited. This type of information is represented by means of integer matrices called Access Pattern Matrices, which are used during the binding phase to efficiently map operations on the LiM architecture. The produced solutions go through further optimization steps that promote the reuse of LiM rows that store intermediate results, in order to reduce area occupation and the needed resources, thus improving the performance of the final circuit. InfoCollector also performs a preliminary code analysis to support the scheduling phase in the management of more elaborated programs. It prunes the code by removing instructions that should not be mapped to the LiM array, and it collects information to detect data dependencies, thus minimizing the scheduler effort and improving its performance. Furthermore, the code emission stage has been enhanced with the introduction of two modules respectively generating enriched configuration files for DEXiMA, and the VHDL description of the final LiM system, with an associated testbench to characterize and simulate the behavior of the proposed solution with standard tools. In order to verify the novelties introduced, algorithms belonging to data-intensive applications have been chosen to be synthesized with Octantis, as they may benefit from the intrinsic parallel capabilities of LiM systems. Information regarding timing, memory size and integrated computational units of the generated architectures has been collected and compared with those obtained without the support of the introduced optimizations. As a result, a noticeable reduction in area occupation has been achieved by up to 16 times, while keeping the execution time as low as possible.

Relators: Mariagrazia Graziano, Giovanna Turvani, Maurizio Zamboni
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 111
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/22828
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