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Design of a RISC-V Based Microarchitecture for Secure Embedded Systems

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Design of a RISC-V Based Microarchitecture for Secure Embedded Systems.

Rel. Paolo Ernesto Prinetto, Gianluca Roascio. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022

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Development In computer system design, an Instruction Set Architecture (ISA) is an abstract model defining the standard characteristic for specific hardware implementation. The term was introduced by IBM around 1970 and from that moment most of the popular ISAs are proprietary standards. Even if, the protection of their intellectual property is understandable, their centralization counteracts innovation and artificially affects the cost of microprocessors. In contrast to this monopoly, there are also several open-source projects. One of the most popular is RISC-V and has started in 2010, as part of the Parallel Computing Laboratory at UC Berkeley under the direction of Professor David Patterson. RISC-V ISA is completely free and open-source, and builds on and improves the original Reduced Instruction Set Computer (RISC). The result is clean, simple, and modular; features that make it suitable for low-power embedded systems and high-performance computers alike. RISC-V was born for study and research purposes, but many companies on the market have started to show interest in implementing their microarchitecture. Considering that, recent open computing standards (like TCP/IP and UNIX) have proved successful allowing free-market competition on technical merit; thus, companies and experts have started to think about the possible benefits of a standard ISA for microprocessors. The CINI Cybersecurity National Laboratory (CNL), in collaboration with the University of Teheran, aims at developing AFTAB, its 32-bit RISC-V-based platform for secure embedded systems. Its core can be used both for research and academic studies, but also allows to make the work on the platform easier. In particular, the development of such a platform allows experimenting both safety and security techniques, adopting the design paradigm known as security-by-design. The aim is to build up a simulation environment combining the RTL design to a software toolchain, and extending it so that it can resist many famouse cyber attacks. The set of instructions supported belongs to the 32-bit base integer ISA variant (RV32I), with multiplication and division extension ("M''). Cross-compilation has been performed setting up the RISC-V-toolchain based on GCC compiler. Custom targets have been also added to automate the RTL compilation running Modelsim commands. The list of instructions belonging to the RV32IM ISA has been completed implementing the missing ones. Moreover, since AFTAB is meant for secure embedded systems, control and status register have been introduced to support user and machine privilege levels. In this regard, the "Zicsr'' instruction set has been added as an extension, together with the modules needed to handle interrupts and exceptions. To verify the correctness of architectural changes, a test automation feature has been added to the toolchain together with some custom test applications in Assembly. To conclude, AFTAB performances have been compared with open-source microcontroller PULPino. The two cores were compared by simulating on both standard benchmarks of the MiBench embedded suite, published by the University of Michigan.

Relators: Paolo Ernesto Prinetto, Gianluca Roascio
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 67
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/22577
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