The difficulties of System on Chip (SoC) verification and debugging have increased at the same exponential rate as Integrated Circuits (IC) hardware complexity. Over the years, design engineers developed different techniques and approaches trying to minimize verification time and reach the highest possible debug coverage. This thesis describes the System Verilog (SV) language fundamental concepts applying Object Oriented Programming (OOP) and the time limits of standard verification methodology. Universal Verification Methodology (UVM) concepts are also detailed explained to show the advantages of this approach. This methodology is based on a hierarchical testbench (TB) structure created by Accelera and gathers reusable code and less debugging time consumption on long-term projects.