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Design of a customizable simulation infrastructure for noisy quantum circuits

Simone Pont

Design of a customizable simulation infrastructure for noisy quantum circuits.

Rel. Maurizio Zamboni, Giovanna Turvani, Mariagrazia Graziano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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Today the availability and the fidelity of real quantum hardware are limited as well as the information that can be directly retrieved from experiments on it. To fully explore the possibilities that quantum algorithms can offer and to reliably estimate the performance of a real quantum computer in a practical scenario, a classical quantum circuit simulator is needed. Following the Dirac notation: noiseless and noisy quantum states and their evolution under quantum gates and non-ideality phenomena, such as decoherence, are described by vectors and matrices composed of complex numbers. The main problem related to this formalism is the exponential increase of both simulation time and memory occupation with the number of qubits. Different approaches for efficiently simulating qubits on classical hardware have been investigated by companies and academic researchers. The goal of this thesis is the development of a quantum circuit simulator capable of handling noisy simulations. The simulator has been developed using the C++ language, which allows greater degrees of optimization in terms of computational cost. Two different representations of quantum states and quantum gates have been explored and implemented: the Array based and the Decision Diagram (DD) based. In the former, quantum states and gates are described using mono and bi-dimensional arrays of the Eigen libraries. In the latter, they are described using graphs that try to optimize the representation by exploiting the redundancies of the elements of vectors and matrices. In both cases, the advantages and disadvantages in terms of performance and memory occupation have been investigated. Regarding the noise contribution, two different simulation approaches have been considered: the classical one, where noise errors are represented using Kraus operators, and an alternative one, based on the compact models for relaxation and decoherence developed at the VLSI Lab of Politecnico di Torino. The introduction of noise errors during the simulation produces a worsening in simulation time and memory usage. This behavior is more evident in the case of DD representation as the noise reduces the redundancies inside the quantum states. The simulator is based on a customizable modular structure that leads to a versatile simulation. Configuration files can be used to change the settings of the simulator, such as the representation or the noise model that have to be used. Moreover, the circuit to be simulated can be defined by hand or by exploiting the OpenQASM 2.0 language. Simple quantum circuits have been employed to compare the different implemented approaches in terms of simulation time and memory occupation. Considering the noiseless simulation, the DD-based representation provides better memory usage results, but it shows longer simulation times. Noisy simulations reflect the same trend, but the obtained performance results are generally worse. Moreover, the noise, limiting the redundancies inside the quantum states exploitable by Decision Diagrams, reduces the differences between the two representations. For this reason, both the memory usage and the simulation time are more similar in the case of noisy simulation. The modular structure of the simulator can be easily improved with new and customized modules, opening the doors to future optimizations. In particular, an improved DD-based structure and the parallelization of the code could allow a reduction of both memory usage and simulation time.

Relators: Maurizio Zamboni, Giovanna Turvani, Mariagrazia Graziano
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 136
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/21112
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