The purpose of this dissertation is to provide an on-chip solution for monitoring and checking in real-time, exploiting event-based sampling to achieve a larger observation window and reduce the amount of time spent during the hardware debugging. The proposed methodology is conceived during a five-month internship at PLDA, which aims to shorten the SoC/ASIC/FPGA development cycles during third-party PCIe PHY integration and validation. With the augmentation of design complexity, the contribution of hardware validation has become extremely relevant. The risk of error is indeed raised because of tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g., crosstalk, line attenuation, jitter, etc.).