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Design and FPGA prototyping of a real-time monitoring unit for the PIPE interface

Nicolo' Rigotti

Design and FPGA prototyping of a real-time monitoring unit for the PIPE interface.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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The purpose of this dissertation is to provide an on-chip solution for monitoring and checking in real-time, exploiting event-based sampling to achieve a larger observation window and reduce the amount of time spent during the hardware debugging. The proposed methodology is conceived during a five-month internship at PLDA, which aims to shorten the SoC/ASIC/FPGA development cycles during third-party PCIe PHY integration and validation. With the augmentation of design complexity, the contribution of hardware validation has become extremely relevant. The risk of error is indeed raised because of tightening timing budgets inside the SoC and electrical issues outside the SoC (e.g., crosstalk, line attenuation, jitter, etc.). Unfortunately, the observability of internal signals during the hardware debugging is extremely limited. In the past years, several hardware debugging methodologies have been implemented to address this problem and, nowadays, the leading FPGA vendors (such as Xilinx and Altera) provide integrated solutions to shorten this process. However, the hardware debugging methodologies currently used present different disadvantages. Embedded Logic Analyzers suffer from tight resource limitations that heavily reduce the observation time window and increase the time needed to track the cause of a malfunction. External Test Equipment is not suitable for pin-constrained design or wide-bus observation. In addition, output pins usually do not support higher bandwidths. Hence, PLDA chose to design a new solution to address these issues and reduce the hardware validation time. In particular, they need a new real-time monitoring unit to observe the PIPE interface. A standard interface defined by Intel that connects the MAC layer (that is located inside of the PCIe Controller) to the PCIe PHY. This dissertation provides some basic knowledge about the PCI Express. Then, it looks at the state-of-the-art hardware debugging methodologies currently employed in the ASIC/FPGA development. It presents the process that aims to identify the system’s constraints and define the key functionalities to implement. Finally, illustrates the development of the hardware IP and of the software application. Since PLDA is particularly interested in monitoring a specific interface (i.e. the PIPE interface), it has adopted an event-based approach. Namely, a set of interesting events is defined and the information is captured and elaborated only when a precise event or error is detected. This process highly reduces the amount of data to store, since it is able to select which information is worth saving. However, a specific-purpose solution is less flexible and it must be designed to be easily modified to support future releases of the PCI Express protocol.

Relators: Guido Masera
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 92
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: PLDA
URI: http://webthesis.biblio.polito.it/id/eprint/21031
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