As the progress in semiconductor industry has led to the realization of increasingly complex circuits able to perform more and more operations in ever shorter times, the power consumption of these circuits is growing rapidly with their complexity, becoming a serious problem to deal with. Since an accurate power estimation requires the presence of a Clock Tree, it is usually performed at the end of the Back End process making almost impossible to modify the original design in order to reduce the power consumption. The purpose of this thesis is to find a design flow able to predict which will be the total power consumption of a circuit not at the end of the design flow but at early design stage giving the possibility to make changes to reduce power consumption as soon as possible.