Giovanni Brignone
Acceleration by Separate-Process Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2021
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Abstract
The end of the Moore’s Law validity is making the performance advance of software run on general purpose processors more challenging than ever. Since current technology cannot scale anymore it is necessary to approach the problem from a different point of view: application-specific hardware can provide higher performance and lower power consumption, while requiring higher design efforts and higher deployment costs. The problem of the high design efforts can be mitigated by the High-Level Synthesis, since it helps improving designer productivity thanks to convenient software-like tools. The problem of high deployment costs can be tackled with Field-Programmable Gate Arrays, which allow to implement special-purpose hardware modules on general-purpose underlying physical architectures.
One of the open issues of HLS is the memory bandwidth bottleneck which limits performance, especially critical in case of memory-bound algorithms
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